Two Phase Clocked Adiabatic Static Logic Circuit: A Proposal for Digital Low Power Applications

This paper proposes a new quasi adiabatic logic family that uses two complementary pulsed supply clock for digital low power applications such as sensors. The proposed two-phase adiabatic static CMOS logic circuit (2PASCL) has switching activity that is lower than dynamic logic and can be directly derived from static CMOS circuits. We have done a SPICE simulation on the chain of four 2PASCL inverters implemented using 0.18 μm CMOS technology. Driving pulse with the height equal to Vdd is supplied to the gates. The results show that 2PASCL can save a maximum of 63.3% of power dissipation over static CMOS logic at transition frequencies of 50MHz to 100MHz. Conventional CMOS vs. 2PASCL When a conventional CMOS which consists of the pull-up and pull down networks connected to a load capacitance CL is set into a logical ‘1’ state, an energy of Eapplied = CLVDD is applied to the load [1]. Energy stored is half of the energy supplied, therefore the total dissipation as heat during charging and discharging is the same as Etotal = CLVDD. Whereas energy dissipation in the channel resistance R is given as Ediss = ( RCL ∆T ) CLVdd . For adiabatic charging, when ∆T , which means the time for the driving voltage to change from 0V to Vdd is long, in theory, the energy dissipation is nearly zero.